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snl320 16-bit lcd controller ======== contents ======== 1. introduction ......................................................................................................................... 5 2. features ............................................................................................................................... .... 5 3. pin assignments .................................................................................................................... 5 4. memory ............................................................................................................................... ...... 6 4.1 i nternal rom .......................................................................................................................... 6 4.2 i nternal ram .......................................................................................................................... 6 5. clock system ........................................................................................................................ 7 5.1 n ormal m ode ........................................................................................................................... 8 5.2 l ow - speed mode ....................................................................................................................... 8 5.3 s top m ode ............................................................................................................................... .. 8 5.4 s uspend m ode .......................................................................................................................... 8 5.5 w atch m ode ............................................................................................................................ 9 6. power on reset .................................................................................................................... 9 7. i/o port ............................................................................................................................... ........ 9 8. timer/counter .................................................................................................................... 10 9. da & push-pull ..................................................................................................................... 11 9.1 dac ............................................................................................................................... .......... 11 9.2 p ush -p ull ............................................................................................................................... 11 10. internal regulator .................................................................................................. 12 11. low voltage detector ............................................................................................ 13 12. ex tension bus ................................................................................................................. 13 12.1 w ord m ode c onnection ...................................................................................................... 14 12.2 b yte m ode c onnection ........................................................................................................ 14 12.3 m aximum m emory e xpend ................................................................................................... 17 12.4 nand f lash i nterface ........................................................................................................ 17 13. usb interface ................................................................................................................. 18 14. lcd interface ................................................................................................................. 18 ver: 1.4 1 april 18, 2006
snl320 16-bit lcd controller 14.1 lcd c ontroller i nterface (8- bit interface ) ................................................................... 18 14.2 lcd d river i nterface (1/4 bits interface ) ....................................................................... 21 14.3 c ontrol s ignals .................................................................................................................... 21 14.4 lcd ram m apping ................................................................................................................ 21 15. application circuit ...................................................................................................... 4 16. absolute max i mum ratings .................................................................................... 4 17. electrical characteristics .................................................................................. 4 18. bonding pad ....................................................................................................................... 5 ver: 1.4 2 april 18, 2006
snl320 16-bit lcd controller amendent history version date description ver 0.1 february 5, 2004 pre liminary spec first issue ver 0.2 march 6, 2004 modify ram size from 6kw -> 10kw in page3 ver 0.3 june 13, 2004 modify pin assignment modify ram size from 10kw -> 11kw in page3 modify int. rom size from 48kw->64kw in page3 modify pin assignments modify extension bus descriptions, add byte/word mode connection add new section ?low voltage detector? and ?internal regulator? ver 0.4 july 28, 2004 wording modifi cation of pin assignment in page 4 ver 0.5 december 7, 2004 1. removed ua rt interface, added usb 1.1 interface 2. reduce internal ram size from 11kw to 8kw (4kw for general purpose, 4kw for lcd display buffer) 3. lcd display only support 120x240 / 4 gray-level lcd display. (lcd ram: 0xb000~0xbfff) 4. move general purpose sram address to 0xa000~0xafff ver 0.6 december 10, 2004 1. page18 corre ct word editing error on lcd ram. ver 0.7 december 14, 2004 1. page21~22 co rrect word editing error on lcd ram. ver 0.8 february 25, 2005 1. correct lcd ram description on page 6 2. modify interrupt sources of ?features? 3. modify pin assignment 4. added another 1k word sram (0x0000~0x03ff), page4, 6, 7 5. added pad information ver 1.0 may 30, 2005 1. modify usb descriptions ver 1.1 june 29, 2005 1. added application circuit 2. correct some error editing on page9 3. correct the clock source option table (page8) 4. remove the rtc 0.125s option (page9) 5. replace pwm instead of push-pull dac (page11) ver 1.2 july 22, 2005 1. correct bonding pad information (p4.2) ver 1.3 july 25, 2005 1. correct bondi ng pad information, pin 113 is ?cksel? and pin111 is ?edws? ver: 1.4 3 april 18, 2006
snl320 16-bit lcd controller version date description ver 1.4 april 18 , 2006 1. delete low clo ck rc source describe (page 5,7,8,9) 2. correct support 4-gray lcd (page 5) 3. add pll = 1 and cksel = 1 is reversed (page 8) 4. add not e : if chi p i s hal t e d , snl320 i n t e rnal r e gul at or will b e d i sab l e (pag e 1 3 ) 5. correct lcd ram size 4k and add note : only support 4mhz lcd clock source (page 22) ver: 1.4 4 april 18, 2006
snl320 16-bit lcd controller 1. introduction the snl320 is a high performance 16-bit dsp base processor with 16mips cpu power. the internal 64k words hi-speed rom already built-in a hi-performance software voice synthesizer to provides lot of voice effects. such as hi-decompression engine to support from 1.5kbps ~ 29kbps compression rate for speech and music, multi-channel voice synthesizer to provides 8-channel wave-table melody, or support foreground 1.5kbps~29kbps and background 4-channel wave-table melody. the standard microprocessor interface allows snl320 to extend its memory capability, or connect external device. we also built-in a low voltage detector circuit for power management and a usb 1.1 interface for communication with pc. 2. features ? power supply: 2.4v ~ 3.6v (for 2 batteries application) 3.6v ~ 5.1v (for 3 batteries application) ? built-in regulator for dsp core ? built-in 16-bit dsp core ? software-based voice/melody processing ? rich function instruction set ? 16 mips cpu performances under 16mhz ? clock sy st em ? 16mhz crystal or r-c type oscillator for hi-speed system clock ? 32768hz crystal oscillator for rtc and low-speed system clock ? extension bus ? standard byte-mode and word-mode bus interface ? 4 chip select pins for external devices (such as rom, flash, sram..etc) ? maximum 128m-bit addressing capability for signal external memory device ? i/o ports: 36 i/o pins (p1.0~p1.15, p3.0~p3.15, p4.0~p4.3) ? rom size: 64k*16 bits ? ram size: 9k*16 bits (including lcd ram) ? 5k*16 sram size for general purpose ? 4k*16 for lcd display buffer ? three 8-bit timers with auto-reload function ? programmable watchdog timer ? lcd control interface ? support 1-bit/4-bit lcd data bus for external lcd driver ? share lcd display ram with internal sram, support 240x120 lcd display screen ? h/w support maximum 4 gray-level lcd display ? built-in 32768 crystal for real time clock ? two voice/melody channels or 4 channels wave-table melody ? built in push-pull direct drive circuit and fixed current d/a output ? sampling rate: 4khz ~16khz ? built-in software voice synthesizer for multiple bit-rate solution ? usb 1.1 interface provided ? low voltage detector ? low voltage reset ? 9 interrupt sources ? 5 internal interrupt (t0, t1, t2, rtc and usb) ? 3 external interrupt (p3.0~p3.2) ? 1 da/push-pull output ver: 1.4 5 april 18, 2006
snl320 16-bit lcd controller 3. pin assignments sy mbol descriptions no. of pin pin count vdda positive power for osc 1 1 vssa negative power for osc 1 2 vddebus positive power for ea0~da22 & ed0~ed15 2 4 vssebus negative power for ea0~da22 & ed0~ed15 3 7 vddio2 positive power for p3.3~p3.15 & p4.0~p4.3 1 8 vssio2 negative power for p3.3~p3.15 & p4.0~p4.3 1 9 ppvdd positive power for push-pull dac 1 10 ppvss negative power for p.p. dac 2 12 vddio1 positive power for p1.0~p1.15 & p3.0~p3.2 1 13 vssio1 negative power for p1.0~p1.15 & p3.0~p3.2 1 14 cvdd positive power for dsp core logic 2 16 cvss negative power for dsp core logic 1 17 rvdd positive power for regulator 1 18 vout regulator voltage output 1 19 pllcap cap pin for pll 1 20 x i n high speed clock crystal input / rc-type oscillator input 1 2 1 x o ut high speed clock crystal output / rc-type oscillator input 1 2 2 lx in low speed clock crystal input 1 23 lx out low speed clock crystal output 1 24 cksel crystal/rc-type oscillator select for high speed clock 1 2 5 pllen pll enable/disable control 1 26 bp0 push-pull da output 1 27 bn0 push-pull da output 1 28 v o 0 d a c o u t p u t 1 2 9 r s t b c h i p r e s e t 1 3 0 test for test only 1 31 ea0~ea22 address bus of extension bus 23 54 ed0~d15 data bus of extension bus 16 70 wr\ write signal of extension bus 1 71 rd\ read signal of extension bus 1 72 edws extension bus width select 0: 8-bit (byte mode) 1: 16-bit (word mode) 1 7 3 d+ usb data + 1 74 d- usb data - 1 75 pwr+ usb power + 1 76 pwr- usb power - 1 77 p1.0~p1.15 general i/o port p1.0~p1.15 16 93 ver: 1.2 5 july 22, 2005
snl320 16-bit lcd controller sy mbol descriptions no. of pin pin count p3.0~p3.15 general i/o port p3.0~p3.15 p3.0: int0 p3.1: int1 p3.2: int2 / ir output p3.3: ncsb p3.4: cle p3.5: ale p3.6: r/b\ p3.7: wpb p3.8: cs3/ea23 p3.9: cs2 p3.10: cs1 p3.11: cs0 p3.12: lacd p3.13: lclk p3.14: lp p3.15: fp 1 6 1 0 9 p4.0~p4.3 general i/o port p4.0~p4.3 lcd data bus 4 1 1 3 4. memory 4.1 internal rom snl320 provides hi-compression algorithm to compress voice data in order to save more memory size. so all the de-compression program are built in the internal rom of snl320 and system will reserved some nec essary rom space for those de-compression program automat ically once user active the de-compression function. there are totally 64k words of snl320 inte rnal rom, user can built-in his own program in the internal rom for his application except necessary space for de-compression program. 4.2 internal ram the internal totally 9k words ram will be s eparated into two parts, the sram regions 0xa000~0xafff and 0x0000~0x03ff are reserved for system and user?s application, the sram regions 0xb000~0xbfff is reserv ed for lcd display buffer. user has to define the actual lcd display buffer region by set lbufl (lcd display buffer register). ver: 1.2 6 july 22, 2005
snl320 16-bit lcd controller lcd buf f e r s t a r t point er 0x a fff lcd di s p l a y b u ffer 0x a 000 4kw no u sed 0x b fff 0 x b000 : : : : : : 0x 0ff f 0x 0000 : : reserv e d for s y stem & u ser 0x 03ff 0x 0 400 : : : : : : : : : : : : free f o r user 4kw 1kw 5. clock sy stem snl320 is a dual clock system that it bot h provides high-speed clock (16mhz) and low-speed clock (32768hz). there two different way to get the hi-speed clock, one is generate by external 16mhz crystal and another way is through external 6mhz pumping to 16mhz by the internal pll circuit. the pin option ?pllen? is used to enable/disable internal pll circuit. 6m h z ros c / x' t a l pl l xi n xo u t 16 m h z p c r . st pm d c k se l pcr . stp c k pll e n s y st e m clo c k l o w - s peed c l o c k l cd dri v e r c l oc k s o urc e / 512 rt c clo c k co ur ce p cr. m c s rc tu ne pcr . stp c k ca p pll e n pcr . rt cc ks figure-1 clock sy stem block diagram ver: 1.2 7 july 22, 2005
snl320 16-bit lcd controller 5.1 normal mode the normal mode means cpu main clock s ource is comes from 16mhz rosc or crystal hi-speed clock source, so snl320 is r un in full speed. there are two pins option ?cksel? and ?pllen? to select rosc/cr ystal and enable/disable pll circuit. the detail setting of hi-speed clock is shown as following table. c k s e l p l l e n d e s c r i p t i o n s 0 0 16mhz x?tal for hi-speed clock source 0 1 6mhz x?tal and pumping to 16mhz for hi-speed clock source. (for usb application) 1 0 16mhz rosc for hi-speed clock source 1 1 r e s e r v e d 5.2 low -speed mode this is a special operation mode of snl320, the hi-speed clock is disable and main clock of snl320 is comes from low-speed clock source (32768hz). it will save more power consumption when chip works on this low-speed mode and this low-speed clock can select 32768hz crystal for clock source. in additional, this low-speed clock also us ed to calibrate the hi-speed clock once the high-speed clock source is comes from rosc. 5.3 stop mode in stop mode, all the system clocks are st op (16mzh & 32768hz) and chip entry a very low power consumption stat e. chip will wake-up from stop mode once any io state change or external interrupt occurs. 5.4 suspend mode in suspend mode, the hi-speed clock still worki ng but chip is hold until any io toggle or external interrupt occurs. that means, the power consumption only come from hxosc circuit and lcd driver interface refresh circuit. ver: 1.2 8 july 22, 2005
snl320 16-bit lcd controller 5.5 watch mode this mode is for some real time clock applic ation, users have to add a 32768hz crystal to realize rtc function. considering to sa ving power consumption, user should stop the hi-speed clock source (16mhz) and enable the low-speed clock source. then chip will entry power down mode but the low-s peed clock still working and wake-up chip once the rtc period is happened in order to fresh the rtc timer. there are four options for rtc interrupt per iod, users can select 0.25sec/0.5sec and 1sec through the rtc control register. if chip is in power-down mode and interrupt enable is active for rtc, then chip will be wake-up from power-down m ode per 0.25/0.5/1 second. 6. power on reset when ?l? level appears on reset pin, t he chip will enter reset state. after reset, the chip does not execute the first instruction until counting 2 17 clock cycles. it takes around 8.2ms at 16mhz. (crystal for clo ck source), and the location of the first instruction after reset is 0x000000. in addi tional, all the contents of sram will be unchanged during reset stage. 7. i/o port snl320 provides totally 36 i/o pins (p1.0~ p1.15, p3.0~p3.15, p4.0~p4.3). the input pull-high resistor of each pin can be programmed by port pull-high register and the direction of i/o port is selected by port direction register. the i/o port p1.0~p1.15 can wake the chip up from the stop mode and watch mode. these 36 programmable i/o pins provides not only a simply input/output function but also can configure to be chip select pins of extension bus, lcd driver interface and nand flash interface. for the detail please refer to following sections. the internal structure of i/o pins is showed in figure-2 . ver: 1.2 9 july 22, 2005
snl320 16-bit lcd controller pu ll- u p r e siste r d a t a l a tch i/ o pa d t o int e rnal bus pu ll- u p se l e ct in / o u t cont rol in / o u t cont rol i/o configuration of port1, port3 and port4 figure-2 in some applications (e.g., infra red, ir), an output port needs to be modulated a carry signal. in the cases, the routine of modulat ion will occupy too many cpu computations. thus, a modulation circuit is built in chip to reduce cpu?s loading. ti me r2 ov er fl o w p3.2 ir en i/o pad figure-3 the modulation function will be active when t he control bit ?iren? set to ?1?. and setting timer2 can generate the frequency of carry signal. 8. timer/counter snl320 provides three 8-bit timer/event c ounters (t0/t1/t2). each timer is 8-bit binary up-count timer with pre-scalar and aut o-reload function. timer 0 (t0) was used when voice playing, so user should avoid to use t0. ver: 1.2 10 july 22, 2005
snl320 16-bit lcd controller auto -r el oa d tn c (8-bit ) syste m cl ock /2 p r e- sca lar enab l e 8-bi t up -co unte r ti me ou t /2 mux com p ara t o r c l ear /4 /8 /2 56 figure-4 9. da & push-pull to play out voices, snl320 contains tw o different solutions for the user?s applications, dac and push-pull. the user can choose one of these two solutions in this design. only one function can be activated at one time. 9.1 dac a 10-bit current type digital-to-analog conv erter is built-in snl320. the relationship between input digital data and output analog cu rrent signal is list ed in the following table. also, the recommended application circuit is illustrated as follows. input data typical value of output current (ma) 0 0 1 3 / 1 0 2 4 ? n n * ( 3 / 1 0 2 4 ) ? 1 0 2 4 3 9.2 push-pull a push-pull direct drive circuit is built-in snl330. the maximum resolution of push-pull is 10 bits . two huge output stage circuits are designed in snl330. with this advanced circuit, the chip is capable of driving speaker directly without external transistors. ver: 1.2 11 july 22, 2005
snl320 16-bit lcd controller vcc buo1/vo 1k buo1/vo buo2 dac output push-pull output 10. internal regulator the power system of snl320 can be separ ated into two groups, one is 3v and another one is 5v. the power of core logi c and sram, rom is co mes from 3v power group. and the power of all i/o, da/push-pull, clock system is comes from 5v power group. considering user?s applicati on, snl320 built-in a regulator to solve the different power problem. please refer to the following connection diagram. 3v cvdd vddi o vo ut _ r e g 5v cv d d vdd i o vo ut _ r e g sn l320 snl3 20 c1 3v pow er sy stem 5v pow er sy stem for 3v power system (2 batteries applic ation), all the power pins should be connected together. ver: 1.2 12 july 22, 2005
snl320 16-bit lcd controller for 5v power system (3 batteries applicati on), the power pin of core logic cvdd pin should be connected to vour_reg in order to get an accurate 2.8v power. once chip entry power down mode, the regul ator will also turn off automatically. and this regulator also built-in a lvd circui t to detect the power dropping of vout_reg. the regulator will auto turn on to re-charge the power of external cap c1 when the voltage of vout_reg is lo wer then 2.2v, it will make sure to provides enough power for cvdd to keep the value of sram. note : if chip is halted , snl320 internal regulator w ill be disable 11. low voltage detector snl320 built in a low voltage detector fo r power management. it provides four different detect level, 2.3v, 2.5v, 2.8v and 3.1v. user can set an expect detect level through the pcr control register and polling the acknowledge bit to get the current power level is higher or lower then the detec t level. each detect level is designed by schmitt trigger architecture, that?s means each detect level has a detect window. for example, the detect window of detect level 2.3v is 2.24v ~ 2.36v. when the vdd power down below 2.24v, the det ect bit of pcr register will be set to 1. once vdd power is recovered and must be higher then 2. 36v, then detect bit is clear by system. detect level voltage w i ndow of schmitt trigger 2.3v 2.24v ~ 2.36v 2.5v 2.44v ~ 2.57v 2.8v 2.72v ~ 2.88v 3.1v 3.01v ~ 3.19v 12. extension bus snl320 built-in a standard micro- controller interface extends the memory capability through the extension bus. in additional, snl320 both provides byte mode and word mode access bus for external memory devic e in order to improve the efficiency. this extension bus also allows users to c onnect different external devices for his own application, such as rom, ram, nand flas h, 8-bit interface lcd controller etc. there are 4 chip select pins for exter nal devices, so totally snl320 can connect 4 different devices. the maximum addressing capability of each external device is 64m-bit except cs0. because the rom bank of cs0 is shared wit h internal rom of snl320, so the maximum addressing capability of cs0 is only 32m-bit. in additional, user can put his program into each ex ternal memory device not only data. ver: 1.2 13 july 22, 2005
snl320 16-bit lcd controller 12.1 word mode connection most of hi-density memory both provides word mode access, so snl320 also support word mode access bus by the pin option ?e dsw?. once the pin ?edsw? is connected to vdd, means the bus width of extens ion bus will turn to be 16-bit width, the connection diagram is shown as bellow. in word mode bus access, snl320 can fetch a complete op code or data through the 16-bit width bus at one time, and it is helpful to improved the cpu efficiency when cpu runni ng the program from external memory device. most important, once the word access is selected, all the data access will fixed at 16-bit mode. so if user connected a 8-bit width external device, the bus pin ed[8..15] of extension bus don?t need to be connected. vdd snl 3 20 e a 0~ea21 ed0 ~ ed1 5 rd \ cs 1 \ edw s vd d oe \ ce\ ed[0..15] ea [0. . 21] 64m f l a sh by t e \ a0 ~ a 2 1 q [ 0..1 5] flash memory word mode connection note: the bit14 of ebcr control register m u st set to be ?1?. 12.2 by te mode connection considering the bus interface of some exte rnal devices and memory are also only 8-bit bus width, so snl320 also support the byte m ode access bus for this kind of device. in byte mode, only data pins ed[0..7] are valid and ed[8..15] are no used. in byte mode connection, snl320 provides tw o different modes for data access, one is 8-bit mode and another is 16- bit mode. the detail description is shown as following section. ver: 1.2 14 july 22, 2005
snl320 16-bit lcd controller 12.2.1 16-bit mode in 16-bit mode, all the data and op code fetch are base on 16-bit data width. in another hand, snl320 will fetch data or op c ode from external memory two times automatically, in order to get a complete 16-bit width data. sn l 3 20 ea0 ~ea22 ed0 ~ ed7 rd \ cs1 \ edw s oe \ ce\ ed[0 . . 7 ] ea[0..22] 64m fla s h by t e \ a[-1~a2 1] q[ 0. .7 ] ed[8 .. 1 5 ] dsp 16-bit mode (for flash by te mode connection) : : : : 0x 00 0000 0x 00 0001 0x 00 0002 byt e 1 0x 00 0003 0x 00 0004 0x 00 0005 : : : : byt e 2 byt e 3 byt e 4 byt e 5 byt e 6 wo r d 1 wo r d 2 rom / flas h/ sr a m re a d f r o m s n l3 20 note: the bit14 of ebcr control register m u st set to be ?1?. 12.2.2 8-bit mode snl320 also reserved a 8-bit mode data acce ss for user?s application. the only one different is the addressing capability of 8- bit and 16-bit mode. in 16-bit mode, the maximum addressing capability of each chip sele ct pin (cs1~cs3) is 64m-bit (cs0 is only 32m-bit) because the address pin ea[22]. in 8-bit mode, the ea[22] is a invalid addr ess pin, so all the addressing capability calculation is only a half of 16-bit mode. ver: 1.2 15 july 22, 2005
snl320 16-bit lcd controller sn l 3 20 ea 0 ~ e a 2 2 ed 0~e d 7 rd \ cs 1 \ edw s oe\ ce \ e d [0..7] ea [0. . 22] m x 29 l v 06 4 by t e \ a[- 1 ~a 21] q[ 0 . . 7 ] ed [8.. 15] dsp 8-bit mode (for flash by te mode connection) : : : : 0 x 000 00 0 0 x 000 00 1 0 x 000 00 2 by t e 1 0 x 000 00 3 0 x 000 00 4 0 x 000 00 5 : : : : by t e 2 by t e 3 by t e 4 by t e 5 by t e 6 by t e 1 r o m / fla s h / sr am byte 2 r ead from s n l3 20 note: the bit14 of ebcr control register m u st set to be ?0?. device no. start address end address memory siz e internal rom 0x0000000 0x000ffff 64k words r e s e r v e d 0 x 0 0 1 0 0 0 0 0 x 0 1 f f f f f 1 9 8 4 k w o r d s 1 st external device 0x0200000 0x03fffff 2m words 2 nd external device 0x0400000 0x07fffff 4m words 3 rd external device 0x0800000 0x0bfffff 4m words 4 th external device 0x0c00000 0x0ffffff 4m words table-1 addressing capability (16-bit mode) ver: 1.2 16 july 22, 2005
snl320 16-bit lcd controller 12.3 maximum memory expend snl320 also provides a special function ext end the memory size from 64m-bit up to 128m-bit for single external device. the ch ip select pin ?cs3? can be turn to the address pin ?a23? once user enable the control bit of ?cs3? & ?ea23? of extension bus control register. d evic e # 3 de v i ce #2 cs 0 \ cs 1 \ cs 2 \ da ta b u s ed[0 ..1 5] a d dre ss b u s e a [0 .. 22 ] de v i c e # 1 ea2 3 ( c s 3 \) ce \ ce \ c e \ a23 snl32 0 12.4 nand flash interface snl320 provides a special function to a ccess data from the external nand flash memory. the following table is shown the relative pins of nand flash memory interface. p3.3~p3.7 will becomes to be the control signal of nand flash memory once the property control register was setting, and data bus of nand flash memory are shared with the data bus d0~d7 of extension bus. all the data read/write are easy to implement by the software. i/o pin pin name direction descriptions p3.3 ncsb o nand flash memory chip enable pin p3.4 cle o command latch enable p3.5 ale o address latch enable p3.6 r/b\ i nand flash memory ready / busy output p 3 . 7 w p b o write p r o t e c t r d \ r d \ o r e a d s i g n a l w r \ w r \ o write s i g n a l ed0~ed7 d0~d7 io data bus d0~d7 ver: 1.2 17 july 22, 2005
snl320 16-bit lcd controller ed 0 ~ ed 7 i/ o 0 ~ i /o 7 re \ we \ ce \ al e cl e r/ b \ rd \ wr \ nc s \ al e cle r/ b \ sn l3 2 0 na n d fl ash wp \ wp \ 13. usb interface the snl320 provides a usb 1.1 interface, user can download/upload data from/to pc through this usb interface. it is support control transfer and bulk transfer. snl320 provides twin buffers for data or command transition and the buffer size of those twin buffers is 64bytes. 14. lcd interface 14.1 lcd controller interface (8-bit interface) the extension bus of snl320 s upports not only external memory device but also 8-bit 8080/6800 microprocessor interface for external lcd controller which already built-in lcd display ram. user should enable ext ension bus before driving external lcd driver, and define the chip select pin y ou used to connect to lcd driver in ebc register. in 8-bit interface lcd controller, lcd disp lay data is stored in lcd controller. any change of lcd display is sent out to ex ternal lcd driver?s ram by addressing different sram space. the interface em ulates the 8080/6800-series interface to speed up the interface data moving processing. figure-5 and figure-6 are the timing diagrams between snl320 and lcd controller by using 8-bit 8080/6800 interface. ver: 1.2 18 july 22, 2005
snl320 16-bit lcd controller 8080-series interface : a0 d0~d7 (write) d0~d7 (read) wr, rd cs figure-5 6800-series interface : e d0~d7 (write) d0~d7 (read) a0 r/w cs figure-6 ver: 1.2 19 july 22, 2005
snl320 16-bit lcd controller figure-7 and figure-8 show out the system connecti on of 8080/6800 lcd interfac es between snl320 and lcd controller. a [ 0. . 21] d[ 0. . 1 5] rd e a [ 0. . 21] ed[ 0 .. 7] cs 0 cs 1 addres s bus data bus me m o r y cs 2 cs 3 a0 d[ 0. . 7 ] lcd control l e r s n l320 wr ce \ wr \ rd\ rd\ wr \ cs 1 8080 lcd controller interface figure-7 a[0..21 ] d [ 0. . 1 5] rd\ ea[0..21 ] d[ 0. . 15] cs 0 cs 1 add r ess b u s data b u s mem o r y cs 2 cs 3 a0 d[ 0. . 7 ] lcd contr o ller snl320 wr \ ce \ wr \ rd\ e wr cs 1 6800 lcd controller interface figure-8 ver: 1.2 20 july 22, 2005
snl320 16-bit lcd controller 14.2 lcd driver interface (1/4 bits interface) snl320 supports not just 8-bit interface but al so 1-bit/4-bit interface for lcd driver. for this kind lcd driver doesn?t include display ram. all the display data is stored in host cpu. so snl320 has to specify a dedicate interface to drive lcd driver. besides, snl320 reserves 4k words lcd buffer (0xb000~0xbfff) for lcd display. hardware circuit will send accurate signal to lcd driv er automatically once the 1-bit/4-bit lcd driver interface is enabled. the inter nal 4k words sram can support maximum 240x120 dots lcd display with 4-grey level effect. note : only support 4mhz lcd clock source 14.3 control signals p3.12~p3.15 & p4.0~p4.3 can be configured to be 1-bit/4-bit interface for lcd driver just by property setting control register. table-2 shows the relation between p3.12~p3.15, p4.0~p4.3 and lcd driver interface. i/o pin pin name descriptions p3.12 lacd lcd alternating signal p 3 . 1 3 l c l k d o t c l o c k p 3 . 1 4 l p l i n e s i g n a l p3.15 fp first line marker p4.0 ld0 lcd data output d0 p4.1 ld1 lcd data output d1 p4.2 ld2 lcd data output d2 p4.3 ld3 lcd data output d3 table-2 14.4 lcd ram mapping the ram region from 0xb000 to 0xbfff totally 4k*16 is reserved for lcd display buffer, user just need to copy the lcd disp lay pattern data into this area then chip will display the pattern on lcd panel automatically. there is a special register lbuf to spec ify the lcd display buffer start address. calculating formula of start address 49152-(seg numbe/16)*com number => for b/w 49152-(seg numbe/16)*com number*2 => for 4 gray levels note: seg number must be the multiple by 8. ver: 1.2 21 july 22, 2005
snl320 16-bit lcd controller for b/w lcd display, each bit of display memory mapping to a pixel in the lcd panel. please refer to following diagram, the disp lay data of seg0 ~ seg 15 at com0 is mapping to bit0~bit15 of display memory 0xb000 0x b 000 se g 0 seg1 se g 2 se g 3 se g 1 5 seg1 6 seg1 7 seg1 8 seg1 9 seg3 1 0x b 001 co m 0 co m 1 se g m com n lcd screen format (b/w) for 4-gray level lcd display, each display pi xel takes two bits space to store the gray level display data. please refer to followi ng diagram, the displa y data of seg0 ~ seg7 at com0 is mapping to bit0~bit 15 of display memory 0xb000. 0x b 000 seg 0 se g1 seg 2 seg 3 seg 7 se g1 0 se g1 1 se g1 5 0x b 001 com 0 com 1 se gm com n seg 8 seg 9 lcd screen format (4-gray level) ver: 1.2 22 july 22, 2005
snl320 16-bit lcd controller 15. application circuit vdd4.5v ld1 ld0 ed12 ed13 ed15 rd\ wr\ v dd3v c4 0.1uf rd\ u1 snl320 cvdd 106 cvdd 100 vdda 6 vssa 1 ea0 29 ea1 30 ea2 31 ea3 32 ea4 34 ea5 35 ea6 36 ea7 37 ea8 38 ea9 39 ea10 40 ea11 41 ea12 42 ea13 43 ea14 44 ea15 45 ea16 46 ea17 47 ea18 50 ea19 51 ea20 52 ea21 53 ea22 54 vddebus 17 vddebus 48 p1.0 82 p1.1 83 p1.2 84 p1.3 85 p1.4 86 p1.5 87 p1.6 88 p1.7 90 p1.8 91 p1.9 93 p1.10 94 p1.11 95 p1.12 96 p1.13 97 p1.14 98 p1.15 99 vddio1 92 vssio1 89 p3 .0 /in t0 81 p3 .1 /in t1 80 p3 .2 /in t2 79 p3 .3 /n c s b 73 p3 .4 /c l e 72 p3 .5 /al e 71 p3 .6 /r b 70 p3 .7 /w pb 69 p3 .8 /c s3 68 p3 .9 /c s2 67 p 3 . 10/ cs 1 66 p 3 . 11/ cs 0 65 p 3 . 12/ la cd 63 p 3 . 13/ lclk 62 p 3 . 14/ lp 60 p 3 . 15/ f p 59 p4 .0 /l d 0 58 p4 .1 /l d 1 57 p4 .2 /l d 2 56 p4 .3 /l d 3 55 ed0 9 ed1 10 ed2 11 ed3 12 ed4 13 ed5 14 ed6 15 ed7 16 ed8 19 ed9 20 ed10 21 ed11 22 ed12 23 ed13 24 ed14 25 ed15 26 wr 27 rd 28 vssebus 33 vssebus 18 vssebus 49 v ddi o2 61 vssio 2 6 4 xin 2 xout 3 lxin 4 lxout 5 vo0 7 pllcap 8 edws 111 pllen 113 cksel 112 vout 107 regvdd 105 rstb 109 vssio 108 test 110 ppvss 74 bp0 75 ppvdd 76 bn0 77 ppvss 78 pwr+ 101 d+ 102 d- 103 pwr- 104 cs1\ vdda y1 6m hz c8 15pf c2 0.1uf c3 0.1uf c 1 1 1 5 p f y2 32768hz c 1 2 15pf c 1 4 1 5 p f ea21 r1 220k vdd3v c6 0.1uf vdd3v rstb rstb p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.7 p1.6 ea0 vdd3v ea1 ea2 ea3 ea4 ea5 ea6 ea7 ea8 ea11 ea9 ea10 ea12 ea13 ea14 ea15 ea16 ea17 ea18 ea19 ea21 ea20 ea22 ed2 ed1 ed0 ed6 ed3 ed5 ed4 ed7 ed10 ed9 ed14 ed8 ed11 lcd display u4 4-bit lcm ld0 la cd lclk lp fp vc c gnd ld1 ld2 ld3 v dd3v la cd lclk lp ld2 ld3 cs 1\ ld0 ld1 fp vdd3v c5 0.1uf c18 47uf c1 0.1uf cvdd c7 0.1uf ea0 vdda ed0 ed1 ed8 ed9 ed2 vdd3v ed3 ed11 ed10 ed4 ed12 ed5 ed13 vdd3v ed6 ed15 ed14 ed7 ea16 ea8 ea11 ea9 ea10 ea14 ea15 ea12 ea13 c13 0.1uf ea18 wr\ ea20 ea19 tr1 ea1 tr3 tr2 tr4 vdd3v ea2 ea3 ea4 ea6 ea7 ea5 ea17 p1.0 p1.2 r5 10 p1.1 p1.3 vdd3v cvdd gnd c15 47uf r4 10 c16 0.1uf cgnd cgnd c17 0.1uf vdd3v r6 1.5k r7 27 r8 27 u3 rt9169 vin 2 gnd 1 vout 3 c22 0.1uf usbd- usbd+ c23 47uf c25 0.1uf speaker c24 0.1uf vdd3v vdd3v d- d+ vdd4.5v c21 4.7uf d- usbpwr- usbpwr- d+ vdd3v j1 usb connector 1 2 3 4 r3 10 vdd3v gnd vdda c9 47uf r2 10 c10 0.1uf gnda gnda fp c20 0.1uf lp c26 0.1uf c19 0.1uf vdd3v u2 mx29lv640t/b a15 1 a14 2 a13 3 a12 4 a11 5 a10 6 a9 7 a8 8 a19 9 a20 10 we_ 11 reset_ 12 a21 13 wp_/acc 14 ry/by_ 15 a18 16 a17 17 a7 18 a6 19 a5 20 a4 21 a3 22 a2 23 a1 24 a0 25 ce_ 26 gnd 27 oe_ 28 q0 29 q8 30 q1 31 q9 32 q2 33 q10 34 q3 35 q11 36 vcc 37 q4 38 q12 39 q5 40 q13 41 q6 42 q14 43 q7 44 q15/a-1 45 gnd 46 byte_ 47 a16 48 lclk vdd3v la cd ld3 ld2 ver: 1.2 4 july 22, 2005
snl320 16-bit lcd controller 16. absolute maximum ratings items sy mbol min max unit. supply voltage v dd - v - 0 . 3 6 . 0 v input voltage v in gnd-0.3 v dd + 0 . 3 v operating temperature t op 0 5 5 o c storage temperature t stg - 5 5 . 0 1 2 5 . 0 o c 17. electrical characteristics item sy m. min. ty p. max. unit condition operating voltage v dd 2 . 4 - 3 . 6 v v dd 3 . 6 - 5 . 1 v standby current i sby - 2 . 0 - u a v dd =3v, no load operating current i op r - 1 0 - ma v dd =3v, no load pull-up resistor of p1, p3, p4 r pu - 8 0 0 - k ? v dd =3v, no load input current of p1, p3, p4 i ih - - 10.0 u a v dd =3v,v in =3v drive current of p1, p3, p4 i od - 6 - m a v dd =3v,v o =2.4v sink current of p1, p3, p4 i os - 8 - m a v dd =3v,v o =0.4v drive current of buo1 i od - m a v dd =3v,buo1=1.5v sink current of buo1 i os - ma v dd =3v,buo1=1.5v drive current of buo2 i od - ma v dd =3v,buo2=1.5v sink current of buo2 i os - ma v dd =3v,buo2=1.5v oscillation freq. (crystal) f os c - 1 6 . 0 - mhz v dd =3v ver: 1.2 4 july 22, 2005
snl320 16-bit lcd controller 18. bonding pad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 10 0 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 10 9 11 0 11 1 11 2 11 3 ( 0 . 0 0, 0. 0 0 ) vs s a xi n xout lxin lxout vd d a vo 0 pllca p ed 1 vd d e b u s v s s ebu s ed 9 wr \ rd \ ea 1 v sse bu s vd de b u s vs se bu s ea 0 ea 2 ea 3 ea 4 ea 5 ea 6 ea 7 ea 8 ea 9 ea 1 0 ea 1 1 ea 1 2 ea 1 3 ea 1 4 ea 1 5 ea 1 6 ea 1 7 ea 1 8 ea 1 9 ea 2 0 ea 2 1 ea 2 2 ed 0 ed 3 ed 2 ed 5 ed 4 ed 7 ed 6 ed 8 ed 1 1 ed 10 ed 13 ed 12 ed 15 ed 14 ver: 1.2 5 july 22, 2005
snl320 16-bit lcd controller disclaimer the information appearing in sonix web pages (?this publication?) is believed to be accurate. however, this publication could contain tec hnical inaccuracies or typographical errors. the reader should not assume that this pub lication is error-free or that it will be suitable for any particular purpose. sonix makes no warranty, express, statutory implied or by description in this publicat ion or other documents which are referenced by or linked to this publication. in no event shall sonix be liable for any special, incidental, indirect or consequential damages of any kind, or any damages whatsoever, including, without limitati on, those resulting from loss of us e, data or profit s, whether or not advised of the possibility of damage, and on any theory of li ability, arising out of or in connection with the use or performance of this publication or other documents which are referenced by or linked to this publication. this publication was developed for products offered in taiwan. sonix may not offer the products discussed in this document in other countries. information is subject to change without notice. please contact sonix or its local representative for information on offerings available. integrat ed circuits sold by sonix are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. the application circuits illustrated in this document are for reference purposes only. sonix disclaims all warranties, including the warranty of merchantability or fitness for any purp ose. sonix reserves the right to halt production or alter the specificati ons and prices, and discontinue marketing the products listed at any time without notice. accordingly, the reader is cautioned to verify that the data sheets and other informa tion in this publication are current before placing orders. products described herein are intended for use in normal commercial applications. applications involving unusual environmental or reliability requirem ents, e.g. military equipment or medical life support equipm ent, are specifically not recommended without additional processing by sonix for such application. ver: 1.2 6 july 22, 2005

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